Prior art electrostatic discharge (ESD) protection devices have been utilized for protecting integrated circuits from being damaged by the high voltage of ESD events. Silicon controlled rectifier (SCR) circuits have emerged as the preferred mode of protecting integrated circuits from ESD events. An SCR is a device which can quickly switch from a high impedance blocking mode to a low impedance shunting latch mode when ESD events are encountered. SCRs are fabricated as an integral part of the integrated circuits.
Recent advances in integrated circuits have included the further development of silicon-on-insulator (SOI) technology, in which an insulator layer is embedded within a substrate and extends beneath the active regions of an integrated circuit. A problem arises since SCRS, the preferred device for protecting against ESD events in integrated circuits, are not suitable for use in SOI integrated circuits. Prior art SCRs typically included two transistors, a PNP transistor and an NPN transistor, which were formed into a substrate, such as a P-type of substrate. The substrate provided a common region of the two transistors, providing the base of one transistor and the collector of the other transistor. Prior art SCRs also typically included a well, such as an N-well, which also provided a common region of the two transistors, providing the base of one transistor and the collector of the other transistor. This arrangement of shared regions between the PNP and NPN transistors caused prior art SCRs to go from a nonconductive, blocking mode when a trigger voltage was applied to the SCRS, to latch in a conductive, shunting mode until the voltage applied thereto fell beneath a holding voltage. Prior art SCRs can not readily be realized in SOI circuits since the portion of the substrate above the embedded insulator layer is relatively thin such that field oxide insulators extend through the top layer of substrate to the embedded insulator layer. Also, N+ and P+ regions typically extend through the top layer of substrate such that embedded resistors cannot be formed between doped regions separated by another doped region.